Technical Field
The present invention relates to a semiconductor wafer, a method of producing a semiconductor wafer, an electronic device, and a method of producing an electronic device.
Related Art
Japanese Patent Application Publication No. 10-313096 discloses a complementary semiconductor device in which an n-type field-effect transistor, an i-GaAs separation layer, and a p-type field-effect transistor are stacked on a GaAs wafer.
A complementary device having an n-type field-effect transistor and a p-type field-effect transistor formed on a single base wafer is expected to serve as an electronic device capable of achieving lower power consumption and high-speed operation.
In the conventional art, a p-GaAs layer is provided to be used as a contact layer under the layer in which the n-type field-effect transistor is formed. Since carriers are allowed to freely move in the p-GaAs layer, the carriers injected from the electrode provided on the contact layer of the p-type field-effect transistor move toward the n-type field-effect transistor through the p-GaAs layer. Consequently, leakage currents flow between the n-type field-effect transistor and the p-type field-effect transistor. This makes it difficult to increase the withstand voltage between the n-type field-effect transistor and the p-type field-effect transistor.
According to the invention disclosed in Japanese Patent Application Publication No. 10-313096, a buffer layer, a p-type channel layer, an i-type barrier layer, a separation layer, an n-type channel layer, an i-type barrier layer, and an n-type contact layer are formed by crystal growth in the stated order on a base wafer in a reaction chamber, and the resulting semiconductor wafer is then removed from the reaction chamber. Subsequently, the layers from the n-type contact layer to the separation layer of the removed semiconductor wafer are subjected to etching to expose a region in which the p-type field-effect transistor is to be formed. After this, the resulting semiconductor wafer is loaded into a reaction chamber to form by crystal growth p-GaAs on the surface of the i-type barrier layer. As described above, the semiconductor device disclosed in Japanese Patent Application Publication No. 10-313096 is produced in accordance with the method in which the semiconductor wafer is removed from the reaction chamber, further processed, placed back into the reaction chamber to perform further crystal growth. This method disadvantageously increases the cost of producing the semiconductor device.